1. Field of the Invention
The present invention generally relates to technology to improve data reliability of flash memory. More specifically, the present invention relates to technology to improve data reliability of flash memory mainly in ICs such as microcomputers having built-in flash memories.
2. Background Information
In conventional ICs such as microcomputers (referred to as MICOMs hereafter) that have built-in flash memories, error checking and correcting circuits (referred to as ECC circuits or EECs hereafter ) have been provided. The reason is that stored data are susceptible to change by disturbances from outside the memory when data-retention, data-write, or data-read is done. Especially, when a flash memory is used as a memory device for operation programs of MICOMs, a malfunction never fails to occur even if a CPU receives just one error bit, and then a checkbit for error checking is stored in addition to the data itself at every address in the flash memory. For example, a six-bit width checkbit is added to 32-bit width memory data.
After receiving the memory data and checkbits, the ECC circuit conducts one-bit error correction or more-than-two-bit error checking and sends the data to the CPU. An example of this final ECC circuit is shown in Japanese Patent Application Publication 2000-20409, which is hereby incorporated by reference.
However, a conventional ECC circuit, which adds a six-bit width checkbit to 32-bit width memory data, has a problem in that it can do one-bit error correction but not more-than-two-bit error correction. A problem arises because a malfunction occurs in a MICOM using a built-in flash memory as a memory device of the CPU programs when a more-than-two-bit error occurs.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved error correction circuit. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.